搜索资源列表
vhdl_source
- MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
AVR_Core8F.tar
- AVR IP core writen in VHDL. It is beta version, working even with AVR studio
bluetooth.tar
- 蓝牙的一个ip RTL 核，不知道对大家有没有用？谢谢。-this is an IP core of blutooth.
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
cyc2_cmon_080805
- Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
8051IP
- Standard 8051 IP Core
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
I2C
- IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境
slaveController
- 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
vga_geometry_xps92i_s3_v01_00_03
- Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color an
fequency
- 一款可用于数字频率计设计的IP核,使用该IP核科研构建基于SOPC技术的片上数字频率计，测频范围较宽。-A digital frequency meter using IP core
cpu86
- CPU86 8086. IP core.
spimaster
- SPI IP core supporting SD/MMC
i2c_master_slave_core
- I2C master/slave IP core
uart_serial
- UART IP core in VHDL
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
aes_core
- aes_core verified verilog ip core-aes_core verified verilog ip core